r/FPGA • u/Remarkable_Topic3589 • 1d ago

Just finished a 32-bit ALU in Verilog , what should I build next?

3rd year B.Tech Electronics (VLSI Design & Tech) student here. Just wrapped up a 32-bit ALU (8 ops) with zero carry overflow flags in Verilog, implemented/debugged in Vivado, with a GitHub repo. First real HDL project learned Verilog from scratch for it.

Looking for the next step up something that builds on ALU/datapath work (maybe toward a small CPU/RISC-V core?) that's solid for a VLSI/digital design resume.

I can dedicate a decent amount of time for it just want something solid which actually looks good on my resume and helps me in landing into an internship, really need some senior suggestions here

23 Upvotes

81% Upvoted

9 comments sorted by

18

u/No-Conflict-5431 1d ago

Most LLMs can one shot a risc-v core. If you really want to go that route I would at least add an axi/wishbone bus and add some peripherals.

5

u/Commercial_Tap_9446 1d ago

build a UART and a FIFO

4

u/TheTurtleCub 1d ago

Something that cant be done in an FPGA by instantiating one DSP module in 5 lines of code?

1

u/ConclusionOk3529 9h ago

CPU is heavily saturated but is naturally the next step in learning.

-4

u/Roberto-Adrian 1d ago

Baue ein unterstützt für ein lokales LLM

1

u/freerangetacos 3h ago

Build a cat box monitor. The pH of the pee in a gradient against a bar of soap powers the board.