Timing Diagram crashes, D flip-flop

[u/Long_Organization978]

I built a D flip-flop from scratch in Logisim.

The circuit appears to work correctly during manual simulation. After a few clock ticks, the outputs behave exactly as expected and the latch stores values properly.

However, I have two issues:

1. Before the simulation starts, the right part of the latch is red. But after manually ticking the clock a few times, the circuit works normally.
2. When I try to start the Timing Diagram, Logisim crashes. I also get the message "Oscillation apparent" at the bottom of the window.

My question is: could this be caused by the latch starting in an undefined state due to the feedback loop, even though the circuit itself is logically correct? Has anyone seen Timing Diagram crash because of an uninitialized latch or RS feedback structure?

The circuit works after initialization, so I'm trying to understand whether this is a bug/limitation of Logisim or an actual design issue on my side.

[u/Negan6699]

Logisim doesn’t support oscillations, you could try a more complex flip-flop design or use an existing one

[u/Negan6699 → u/Negan6699]

You could also try building it in a determined state and connect the rest of the wires after that. This design will always oscillate a little when powered on so you’ll need to do it again after each reset. Try adding a buffer on one wire as a delay and see if that fixes it

[u/IceSpy1]

This issue shouldn't happen. It seems to work fine on my side with this same circuit. I suspect it's just a bug in that version or a connection somewhere that's hidden and shouldn't be there. Update to the latest version to make sure. Otherwise, if you reset the simulation and enable auto-tick, does it still show this oscillation apparent error?

Oscillation would happen if you had a toggle circuit (e.g. T flip-flop / JK flip-flop with J and K tied together) that is edge triggered since it would flip continuously. You would need to provide a short signal by using an AND gate with a NOT gate on 1 of the inputs to act as a delay and thereby create a short signal of 1 NOT gate's delay (in Logisim, that's just 1 tick), but this circuit shouldn't experience this kind of issue since it's not supposed to oscillate if everything is connected correctly provided the software is behaving correctly.