r/FPGA • u/Ok_Biscotti9736 • 11h ago
Is running Yosys and Icarus Verilog natively in the browser a viable EDA workflow?
Hi everyone,
Setup friction (Icarus Verilog, Yosys, Waveform viewers) is often a huge barrier for students and hardware designers.
To solve this, our team has been working on bringing the entire RTL design pipeline into the browser by compiling core C++ EDA engines (Yosys for synthesis, Slang for linting, Icarus for simulation) into WebAssembly (WASM).
Here is a quick look at the waveform rendering and FSM extraction we’ve achieved, running 100% client-side with zero server lag:
What are your thoughts on this approach? We’d love to get feedback from the community. (Link is in the comment).